1. Field of the Invention
An aspect of the present invention relates to an electrically rewritable semiconductor memory and in particular to a nonvolatile semiconductor memory.
2. Description of the Related Art
Demand for small-sized and large-capacity nonvolatile semiconductor memory grows sharply. Among the nonvolatile semiconductor memory, particularly, flash memory is used in various applications and a request is made for putting flash memory into a further larger capacity. Microminiaturization of the flash memory is acceleratively advancing, and thus a physical limit of the microminiaturization is being approached. With a structure where memory cells, circuit elements, etc., are placed on a flat face as in the current flash memory, enhancement of the capacity of the flash memory is realized by further microminiaturization. However, there are limits of the microminiaturization.
In recent years, to enhance the integration degree of memory, a large number of semiconductor memories each with memory cells placed three-dimensionally have been proposed. (For example, refer to JP-A-2003-078044, U.S. Pat. No. 5,599,724, U.S. Pat. No. 5,707,885 and Endo et al., “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, N04, pp 945-951, April 2003.)
In many related-art semiconductor storage devices including three-dimensionally arranged memory cells, memory cells must be subjected to a plurality of photo engraving processes (hereinafter abbreviated as “PEP,” wherein patterning is performed through processes, such as a lithography process and an etching process, employing a so-called photoresist) on a per-layer basis. A PEP which is performed at a minimum line width of the design rule is taken as a “critical PEP,” and a photo engraving process which is performed at a line width greater than the minimum line width of the design rule is taken as “rough PEP.” In a related-art semiconductor storage device in which memory cells are arranged in a three-dimensional pattern, three critical PEPs or more are required for one layer of memory cell. Moreover, in many semiconductor storage devices, memory cells are simply stacked one on top of the other, which unavoidably results in an increase in cost attributable to three-dimensional integration of memory cells.
Additionally, in a case where the memory cells are arranged in a three-dimensional pattern, a cost reduction effect can be enhanced if all via holes for a plurality of word-line electrode layers (such as, a polysilicon layers, an amorphous silicon layers or metal layers) of the memory cells can be formed in one process.